1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Background Art
In a semiconductor device, a parasitic element that exerts an action different from an intended action may be formed depending on an internal configuration, resulting in a parasitic action. The parasitic action adversely affects an original action of the semiconductor device, and hence there have conventionally been studied various configurations of the semiconductor device to suppress the parasitic action.
Japanese Patent Laying-Open No. 09-293729 discloses a semiconductor device in which an N-type epitaxial layer is formed on a P-type silicon substrate, and a P-type region is formed in the N-type epitaxial layer to penetrate the same in a vertical direction to change the N-type epitaxial layer into islands separated in an insulated manner. It is disclosed therein that, in the semiconductor device, the islands are used to form an NPN bipolar transistor, and that the semiconductor device is irradiated with protons from a surface side of the P-type silicon substrate to form a carrier recombination layer in the P-type silicon substrate.
Japanese Patent Laying-Open No. 58-077254 discloses a logic integrated circuit device including a P-type monocrystalline silicon substrate coupled to a negative power supply potential, a first N-type epitaxial region located at a surface of the silicon substrate and having a logic signal input therein, a second N-type epitaxial region located at the surface of the silicon substrate to be spaced apart from the first N-type epitaxial region and coupled to the negative power supply potential, a third N-type epitaxial region located at the surface of the silicon substrate to be spaced apart from the first and second N-type epitaxial regions, coupled to a positive power supply potential via load-resistor means, and turning to logic “1” if the first N-type epitaxial region is at logic “0”, and a P-type separation region separating the first, second, and third N-type epitaxial regions from one another in an insulated manner.
Japanese Patent Laying-Open No. 59-094861 discloses a semiconductor integrated circuit device including a semiconductor layer formed on a first conductivity-type semiconductor substrate and having an approximately uniform concentration distribution of prescribed conductivity-type impurities, a second conductivity-type first well region formed at a prescribed site of a surface of the semiconductor layer, a first conductivity-type second well region formed to surround the first well region at the surface of the semiconductor layer, a second conductivity-type first embedded region provided between the first well region and the semiconductor substrate adjacently thereto, and having a higher impurity concentration than the first well region has, a first conductivity-type second embedded region provided between the second well region and the semiconductor substrate adjacently thereto, and having a higher impurity concentration than the second well region has, and an active element formed in each of the first well region and the second well region.
In a semiconductor device, one conductivity-type region, the other conductivity-type region, and the like are formed at a substrate to configure various elements. As described above, the regions of the respective conductivity types are formed in proximity to one another, and hence there may occur a parasitic action, which is different from the original purpose.
An example of the semiconductor device is a bipolar transistor formed at a surface of the semiconductor substrate. Among the bipolar transistors, an npn bipolar transistor is formed such that an n-type semiconductor region, a p-type semiconductor region, and an n-type semiconductor region are formed at a surface of a p-type semiconductor substrate. In such a transistor, a parasitic transistor is also configured inside the semiconductor substrate, which may cause a parasitic action.